In regard to an electronic circuit such as a large-scale processor performing high-speed processing, the degree of integration has been increased on the one hand, while low power consumption is required on the other, by which LSI design comes to be restricted. Namely, in the electronic circuit of this kind, it is required to satisfy both high frequency and low power consumption.
To realize such low power consumption, in a CPU and a DRAM which require clock, etc. continuously, an operating method with a reduced clock frequency has been introduced, with the provision of a standby mode (For example, refer to Japanese Patent Laid open Publication No. Hei 5-290187 and No. Hei 6-028053). Also, in the logic design technology, efforts have been made to reduce power consumption in an overall LSI, by controlling to securely inhibit the operation, except for when the operation is necessary, with clock supply to the object circuit being suspended (For example, refer to Japanese Patent Laid open Publication No. Hei-11-074466).
The integrated circuit concerned has a variety of circuit elements including diodes, transistors, resistors and capacitors integrated therein. In each individual circuit element, there is fluctuation in the operation thereof, particularly in delay time, caused by fluctuated peripheral environments such as temperature, supply voltage and noise, and fluctuation incurred when manufacturing the circuit element concerned.
Accordingly, when designing an integrated circuit such as processor, usually, considering the fluctuation in the delay time in the circuit elements, marginal design has been adopted to guarantee against the delay time, by assigning the margin using the cases of the operation speed being the highest and the lowest.
In the situation of today, in which higher frequency and lower power consumption are required more and more, peripheral environments of the circuit elements, and previous operation conditions as well, may relatively influence more severely. Therefore, a more accurate marginal value is required for guaranteeing against delay time.
Meanwhile, to guarantee against the delay time, because a wide fluctuation range between the highest and lowest operation speeds of the circuit element is to be taken into account when assigning the margin, it is probable that an excessive margin is assigned for guaranteeing in consideration of the worst case.
As high-speed operation is increasingly required, a severer marginal value is required. However, adoption of new semiconductor technology includes phenomena which are not completely solved. This brings about difficulty in obtaining an accurate margin, and sometimes the margin may fall short. Under such a circumstance, unexpected events may occur, and accurate operation may be impeded.
For example, in the design technology, there has been introduced a trial to realize low power consumption by suspending clock supply to an object circuit except for the time of necessary operation. This causes a state that the transistor, etc. included in the object circuit are not in operation for a long time.
When the transistor is operated, the transistor consumes power, generates heat, produces a varied temperature, or a varied impedance of the transistor, by which an instantaneous variation/reduction (A.C./D.C.-Drop) of the supply voltage is produced. With this, a variety of parameters, such as threshold voltage (Vth), ON current (Ids-ON), OFF current (Ids-OFF), wiring resistance, delay time, are varied.
Thus, when the transistor becomes operated, the peripheral environments, such as the temperature and the supply voltage, become different from those when the transistor is not operated. When a circuit element such as transistor becomes operated after the transistor has not been in operation for a long time, the characteristic of the circuit element varies, and the operation becomes either faster or slower, as compared to the case when the transistor has been in operation continuously. In other words, a larger margin becomes necessary for guaranteeing the operation, and in the actual operation, accurate operation may be impeded.
Further, in the semiconductor technology, an SOI (silicon-on-insulator) has been adopted as an option for satisfying low power consumption. Here, one of the known problems in the SOI is a history effect.
FIG. 22 shows a configuration diagram of a bulk substrate, while FIG. 23 shows a configuration diagram of an SOI substrate. As shown in FIG. 22, in regard to a transistor using the bulk substrate, a drain 101 and a source 102 are disposed in a Si substrate 100, and also a gate 103 is disposed through an insulator (SIO2) 104. Thus the transistor is structured.
Meanwhile, as shown in FIG. 23, as to a transistor using the SOI substrate, a drain 101 and a source 102 are disposed on an insulator (SiO2) 110 being provided on a Si substrate 100, and also a gate 103 is disposed through an insulator (SiO2) 104. Thus, the transistor is structured.
Accordingly, since the transistor is surrounded by the insulator, current leakage caused by a capacitive component can be avoided, thus enabling reduction of the power consumption. Meanwhile, with this, body potential of a body 105 disposed between drain 101 and source 102 becomes in a floating state, which is not electrically fixed. As a result, the body potential fluctuates depending on the previous operational and bias conditions.
Also, since a transistor threshold voltage Vth is influenced by the body potential, the switching operation of the transistor becomes either faster or slower, depending on the previous operational and bias conditions. As factors causing fluctuation of the body potential, there are a short-term factor produced when the transistor is operated and a long-term factor produced when the transistor is not operated.
When the transistor is operated, the body potential is abruptly varied caused by the coupling capacitance thereof. When the transistor is not in operation for a long time, a voltage is applied between two terminals (among gate 103, drain 101 and source 102). This produces an electric field in the vicinity of body 105, causing a gradual variation of the body potential.
The body potential is determined by complicated operation histories in the past, being combined with both short-term and long-term factors. Therefore, it is considered to have a variety of values. Caused by this, the switching operation becomes slow or fast when the transistor becomes operated actually. Namely, similar to the aforementioned case, larger margin becomes required for the operational guarantee, and a case of the accurate operation being impeded may arise in the actual operation.
As such, in the situation that a high frequency and low power consumption are required, and that influences to the circuit elements caused by the peripheral environments and previous operational conditions become relatively critical, it is desired to have a means for reducing or eliminating fluctuation of the delay time produced in the circuit element operation.